LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.controller;

--TESTBENCH DO CONTROLADOR DE ENTRADAS E SAIDAS

ENTITY tb_controller IS
END tb_controller;

ARCHITECTURE logic OF tb_controller IS

COMPONENT controller
    PORT(address: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
        test_state: IN STD_LOGIC_VECTOR(4 DOWNTO 0); 
        pin: OUT STD_LOGIC_VECTOR (13 DOWNTO 1) := (OTHERS => 'Z'));
END COMPONENT;

FOR tb_controller: controller USE ENTITY WORK.controller;

SIGNAL s_pin: STD_LOGIC_VECTOR(13 DOWNTO 1) := "0000000000000";
SIGNAL s_test_state: STD_LOGIC_VECTOR(4 DOWNTO 0):= "00000";
SIGNAL s_addr: STD_LOGIC_VECTOR (9 DOWNTO 0);

BEGIN
    tb_controller: controller
    PORT MAP(address=>s_addr, test_state=>s_test_state,pin(13 DOWNTO 1)=>s_pin(13 DOWNTO 1));
    PROCESS
        TYPE pattern_type IS RECORD
            vi_addr: STD_LOGIC_VECTOR (9 DOWNTO 0);
				vi_test_state: STD_LOGIC_VECTOR(4 DOWNTO 0);
				vo_pin1, vo_pin2, vo_pin3: STD_LOGIC;
        END RECORD;
        TYPE pattern_ARRAY IS ARRAY (NATURAL RANGE <>) OF pattern_type;
            CONSTANT patterns : pattern_ARRAY :=
            (
                ("0000000000", "00000", 'Z', 'Z', 'Z'),
                ("0101010101", "00000", 'Z', 'Z', 'Z'), --no depende de address, apenas test_state
                ("0000000000", "00000", 'Z', 'Z', 'Z'),
                ("0000000011", "00001", '0', 'Z', 'Z'),
                ("0000000100", "00001", '1', 'Z', 'Z'),
                ("0000001001", "00010", '0', '1', 'Z'),
                ("0000001010", "00010", '1', '1', 'Z')						 
             );
    BEGIN
        FOR i IN patterns'RANGE LOOP
            s_addr <= patterns(i).vi_addr;
				s_test_state <= patterns(i).vi_test_state;
            WAIT FOR 100 ps;
				ASSERT s_pin(1) = patterns(i).vo_pin1 REPORT "VALOR DO PINO 1 ERRADO" SEVERITY error;
				ASSERT s_pin(2) = patterns(i).vo_pin2 REPORT "VALOR DO PINO 2 ERRADO" SEVERITY error;
				ASSERT s_pin(3)= patterns(i).vo_pin3 REPORT "VALOR DO PINO 3 ERRADO" SEVERITY error;
        END LOOP;
        ASSERT false REPORT "END of test." SEVERITY note;
        WAIT;
    END PROCESS;
END logic;
